1. Field of the Invention
The present invention relates to generating a command file, and more particularly, to generating a command file of a group of DRC rules and/or a command file of a group of LVS/LPE rules to be used by a layout verification tool.
2. Description of the Prior Art
A computer programmed with layout verification software is normally used to verify that a design of an integrated circuit (IC) chip conforms to certain predetermined tolerances that are required by a process to be used in fabricating the chip, to ensure that a layout connectivity of the physical design of the IC matches the logical design of the IC represented by a schematic, and to extract parasitic resistance and capacitance of the IC. These are all very important steps for guaranteeing the properties of the chip manufactured by the process before the tape out of the circuit.
Tolerances for the process that is used to fabricate the IC, methods for checking the consistency between the physical design and the logical design of the IC, and the way to extract parasitic resistance and capacitance of the IC are often specified in the form of “rules”. In an operation, these kinds of rules are called design rule check (DRC) rules, layout versus schematic (LVS) rules and layout parasitic extraction (LPE) rules respectively. Examples of DRC rules to be used in checking the design of an IC include minimum width, minimum spacing between elements of a circuit, minimum width of notches, checks for acute angles and self-intersecting polygons, and enclosures and overlap checks. Such DRC rules can be applied to actual layers that are to be fabricated in the chip, and also to derived layers that are formed by logical operations (such as not, and, or, and xor) on actual or derived layers or some combination thereof. Running a command file of LVS rules extracts devices and nets formed across layout hierarchy and compares them to the schematic netlist to ensure that a layout connectivity of the physical design of a circuit matches the logical design of the circuit represented by a schematic. For a command file of LPE rules, it helps to verify electromagnetic phenomena due to parasitic resistance and capacitance of the circuit.
With current technologies, command files of DRC rules and LVS/LPE rules used by a layout verification tool to verify the layout and the parasitic characteristics of an integrated circuit become more and more complicated. It is known that the verifications of ICs of different processes or packages require different command files of DRC and LVS/LPE rules. Consequently, the increasing metal options and bonding styles raise the quantity of the demand for command files dramatically. It is not easy to update thousands of lines of program codes manually without mistakes, and the load of maintaining the command files is heavy. In fact, there are a lot of rule statements sharing the same command, and there are some blocks of commands can be shared for different layout verification function. However, with the method for generating command files according to prior art, different command files can only be generated individually. Therefore it costs a lot of time and effort to generate new command files with different parameters even the new command files are only a little different from other existing ones.
There are already lots of such layout verification tools on the market but they all suffer from the aforementioned problems of maintaining program codes. And the generation of a new command file for verifying the fabrication of ICs by different process or of different parameters is very inefficient.